Intel Disables Unsecured TSX Feature on Legacy Processors – Computer


Intel has decided to disable transaction synchronization extensions in the processor chips of Skylake, Kaby Lake, Coffee Lake, and Whiskey Lake processors. Intel disables the feature due to memory arrangement errors and because hackers can exploit it.

Phoronix discovered that TSX will soon be deprecated in a mini CPU update accidentally while reading new kernel patches. Disabling TSX will cause poor performance on older chips on some jobs. TSX adds support for hardware transaction memory to processors, giving them up to 40% better performance on some tasks, according to Intel figures. TSX has been in chips based on the Haswell microarchitecture since the Skylake generation since 2013.

In 2016, it was discovered that TSX can be exploited in a side channel sync attack, in which hackers can break the randomness of a kernel address space layout, or KASLR, to gain access to a system. This is one of the reasons the feature is not supported.

The most important reason, according to Phoronix, is that TSX can cause an error in the memory order, that is, the sequence of memory accesses. Intel published a pdf white paper on this earlier this month. This issue has been known since 2018 and therefore has already been disabled in SGX and SMM. With the partial update, TSX is no longer accessible and there is no workaround in the Linux kernel.

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